1. Field of the Invention
The present invention relates to a semiconductor device used in a light reception circuit section or the like in an optical data link or an optical CATV system.
2. Description of the Related Background
A conventional light reception circuit of this type is shown in FIG. 1, for example. A light signal is received by a light-receiving element 1 and converted into a voltage signal by a resistor R.sub.L. A direct-current component is removed by a capacitor C.sub.C from the reception signal which is converted into the voltage signal, and the reception signal is amplified and demodulated by an amplifier 2. The resistor R.sub.L, the capacitor C.sub.C, and the amplifier 2 are formed on the same integrated circuit (IC) chip 3. Generally, the resistor R.sub.L has a resistance of several hundreds ohms to 10 k.OMEGA., and the direct-current component cutoff capacitor C.sub.C has a capacitance of several pico-farad to several hundreds pico-farad. A junction capacitance C.sub.PD of about 0.5 pF is present in a p-n junction of the light-receiving element 1, a floating capacitance C.sub.CG (to ground) is present in the capacitor C.sub.C, and an input capacitance C.sub.IN is present in an input section of the amplifier 2. When an input resistance of the amplifier 2 is given by R.sub.IN, a high-pass cutoff frequency F.sub.H and a low-pass cutoff frequency F.sub.L of the reception signal are expressed by the following equations, respectively. EQU F.sub.H =1/[2.pi.(R.sub.L //R.sub.IN).multidot.(C.sub.PD +C.sub.IN +C.sub.CG)]. (1) EQU F.sub.L =1/[2.pi.(R.sub.L //R.sub.IN).multidot.C.sub.C ] (2)
FIGS. 2(A) and 2(B) show the inside of a package when the IC chip is packaged. FIG. 2(A) is a plan view of the IC chip, and the FIG. 2(B) is a side view of the IC chip. A common ground pattern 5 which is set at a common reference voltage for the circuit is formed on a ceramic substrate 4, and IC chip 3 is die-bonded on the ground pattern 5 through a back metal formed on the back of the IC chip 3. A reference potential of an inner circuit of the IC chip 3 is set to be equal to a potential of the ground pattern 5 by means of a wire. A signal terminal pattern 6 electrically isolated from the common ground pattern 5 is wire-bonded with external terminals of the IC chip 3 and electrically connected to frame lead pins.
In the above conventional device arrangement, when the resistance of the resistor R.sub.L is increased to improve receiving sensitivity of the circuit, an S/N ratio showing a signal-to-noise ratio is increased, thereby improving the receiving sensitivity. However, as understood from equation (1), the high-pass cutoff frequency F.sub.H is decreased. When the resistance of the resistor R.sub.L is constant, the high-pass cutoff frequency F.sub.H is increased proportional to a decrease in capacitance of (C.sub.PD +C.sub.IN +C.sub.CG).
In order to decrease the low-pass cutoff frequency F.sub.L, as understood from equation (2), when the resistance of the resistor R.sub.L is constant, the capacitance of the direct-current component cutoff capacitor C.sub.C must be large. For this reason, an electrode pattern 7 for the capacitor C.sub.C occupies a large area in the IC chip 3 as shown in FIG. 3. Therefore, the floating capacitance C.sub.CG present between the electrode pattern 7 and the ground pattern 5 is increased, thereby decreasing the high-pass cutoff frequency F.sub.H. In addition, when the capacitance of the capacitor C.sub.C is decreased to decrease the floating capacitance C.sub.CG, the low-pass cutoff frequency F.sub.L is increased, thereby increasing jitter.